Dual threshold digital receiver with large noise margin

ABSTRACT

A receiver circuit has a high threshold of 3.3÷2 volts and maximum noise margin. This is achieved by making two transistors in the receiver have channel resistances, under the condition whereas input line carries 3.3÷2 volts and a control line carries 0 volts, that generate an output signal as a first resistance ratio which when multiplied by a supply voltage equals 3.3÷2 volts. Further, the receiver also has a low threshold of 2.5÷2 volts and maximum noise margin. This is achieved by making the above two transistors, plus two other transistors in the receiver, have respective channel resistances under the condition where the input line carries 2.5÷2 volts and the control signal line carries 3.3 volts, that generate the output signal as a second resistance ratio which when multiplied by the supply voltage again equals 3.3÷2 volts.

This is a of application Ser. No. 08/275, 555 filed on Jul. 15, 1994 nowabandoned.

BACKGROUND OF THE INVENTION:

This invention relates to digital receiver circuits; and moreparticularly, it relates to a novel circuit structure which enables thereceiver to selectively have a high threshold voltage with a large noisemargin or a low threshold voltage with a large noise margin.

Conventionally, digital receiver circuits are used in various types ofdata processing systems where a plurality of digital logic chips areinterconnected to each other. There, the receiver circuit acts as abuffer between the input terminals of a chip and the chip's internaloperating circuitry. For example, one chip may be a microprocessor, andanother chip may be a memory which supplies data to the microprocessor.In that case, the data is sent from the memory to the microprocessor asseveral bits in parallel; and each of those bits is passed through arespective receiver circuit in the microprocessor chip before beingotherwise acted upon.

Each bit of data which is sent to its respective receiver circuit has a“0” voltage level and a “1” voltage level; and ideally, the receivercircuit should have a threshold voltage which is midway between the “0”and “14” voltage levels. By definition, the threshold voltage of thereceiver is the input voltage which causes the receiver output to be athalf of the “1” voltage level. When the receiver circuit has such athreshold voltage, the difference between a “0” input voltage and thethreshold voltage equals the difference between a “1” input voltage andthe threshold voltage; and thus the noise margins on the input signalare as large as possible.

However, in the integrated circuit industry, new chips are continuallybeing developed; and from time to time, a new chip is developed with areduced “1” voltage level in comparison to the pre-existing chips.Recently, the standard “1” voltage level was reduced from 5 volts to 3.3volts. In three to five years, it is likely that new chips will becomeavailable which have a further reduced “1” voltage level of only 2.5volts. After that, new chips are expected to have an even furtherreduced “1” voltage level of only about 1.7 volts.

By reducing the “1” voltage level, the circuitry which is on anintegrated circuit chip can be reduced in size; and thus, a single chipcan contain more circuits per unit area. For example, a memory chipwhich has a “1” voltage level of 2.5 volts can contain more memory cellsthan a memory chip of the same size which has a “1” voltage level of 3.3volts. However, reducing the “1” voltage level of just one particularchip presents a system problem of how to incorporate that chip into apreviously designed system which has other chips that operate at ahigher “1” voltage level.

Suppose, for example, that a new high density memory chip becomesavailable which has a reduced “1” voltage level of 2.5 volts, but no newmicroprocessor chip is available with the same reduced “1” voltagelevel. From a systems viewpoint it would be desirable to use the newmemory chip in order to take advantage of its higher memory density. Butif the new memory chip is used with a pre-existing microprocessor chipwhich has a “1” voltage level of 3.3 volts, then the receiver circuitsin the microprocessor chip will operate with a reduced noise margin.Thus, the resulting system will be susceptible to errors which arecaused by noise on the “1” or “0” voltage levels.

Accordingly, a primary object of the invention is to overcome the aboveproblem by providing a novel structure for a receiver circuit whichselectively has both a high threshold voltage with maximum noise marginand a low threshold voltage with maximum noise margin.

BRIEF SUMMARY OF THE INVENTION

In accordance with the present invention, a dual threshold digitalreceiver circuit is comprised of four transistors. The first transistorand the second are interconnected in series from a voltage supply bus toa ground bus; whereas the third transistor and the fourth transistor areinterconnected in series from the connection between the first andsecond transistors to the ground bus. An input line is connected torespective gates on the first, second, and third transistors; a controlline is connected to a gate on the fourth transistor; and an output lineis connected to the series connection between the first and secondtransistors.

In one embodiment, the receiver circuit has a high threshold of 3.3÷2volts and maximum noise margin. This is achieved by making the first andsecond transistors have channel resistances, under the condition wherethe input line carries 3.3÷2 volts and the control line carries 0 volts,that generate an output signal as a first resistance ratio which whenmultiplied by the supply voltage equals 3.3÷2 volts. Further, thereceiver also has a low threshold of 2.5÷2 volts and maximum noisemargin. This is achieved by making all four of the transistors haverespective channel resistances, under the condition where the input linecarries 2.5÷2 volts and the control signal line carries 3.3 volts, thatgenerate the output signal as a second resistance ratio which whenmultiplied by the supply voltage again equals 3.3÷2 volts.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a dual threshold digital receiver circuit which inaccordance with the present invention is operating with a high thresholdvoltage in response to a control signal CS=“0”.

FIG. 2 shows the dual threshold digital receiver circuit of FIG. 1 whichin accordance with the present invention is operating with a lowthreshold voltage in response to a control signal CS=“1”.

FIG. 3 is a graph which shows how the noise margins in the receivercircuit of FIGS. 1 and 2 are maximized while selecting either the highthreshold voltage or the low threshold voltage.

FIG. 4 is a detailed circuit diagram of one preferred embodiment of thedual threshold digital receiver circuit of FIGS. 1 and 2.

FIG. 5A is an equivalent circuit diagram for the dual threshold digitalreceiver circuit of FIG. 4 under the condition where the control signalis a “0” and the input signal equals the high threshold voltage.

FIG. 5B is a simplification of the FIG. 5A circuit.

FIG. 6A is an equivalent circuit diagram of the dual threshold digitalreceiver circuit of FIG. 4 under the condition where the control signalis a “1” and the input voltage equals the low threshold voltage.

FIG. 6B is a simplification of the FIG. 6A circuit.

FIG. 7 is a table which illustrates several channel width-channel lengthratios which are suitable for two of the transistors in the FIG. 4receiver circuit.

DETAILED DESCRIPTION

Referring now to FIGS. 1-3, the operation of the present invention froma high level systems viewpoint will be described. In FIGS. 1 and 2, adual threshold digital receiver circuit 11 is shown which constitutesone preferred embodiment of the invention; and this receiver circuit 11is contained within an integrated circuit chip 12. Also in both FIGS. 1and 2, an input line to the receiver circuit is indicated by referencenumeral 11 a; an output line from the receiver is indicated by referencenumeral 11 b; and a control line to the receiver is indicated byreference numeral 11 c.

When the control line 11 ccarries a control signal CS which is at alogical “0” voltage level, the receiver circuit 11 operates with a highthreshold voltage V_(TH) which equals 3.3 volts divided by 2. This modeof operation is illustrated in FIG. 1. By comparison, when the controlsignal CS on the control line 11 c is at a logical “1” voltage level,the receiver circuit 11 operates with a low threshold voltage V_(TL)which equals 2.5 volts divided by 2; and this mode of operation isillustrated in FIG. 2.

By having the high threshold voltage V_(TH), the receiver circuit 11 isable to receive a digital input signal v_(i), which has “0” and “1”voltage levels of 0 and 3.3 volts, with the largest noise margin that ispossible. This is illustrated in FIG. 1 wherein the 0 and 3.3 voltdigital input signal is generated on the input line 11 a by atransmitter 20.

Likewise, by having the low threshold V_(TL), the digital circuit 11 isable to receive a digital input signal which has “0” and “1” voltagelevels of 0 and 2.5 volts with the largest noise margin that ispossible. This is illustrated in FIG. 2 wherein the 0 and 2.5 voltdigital input signal is generated by a transmitter 21.

Each of the above noise margins are further illustrated in FIG. 3.There, a graph is provided wherein the input voltage v_(i) to thereceiver circuit 11 is plotted on a horizontal axis; and the outputvoltage v_(o) from the receiver circuit 11 is plotted on a verticalaxis. In that graph, a curve 31 shows how the output voltage v_(o)varies as a function of the input voltage v_(i) when the control signalCS is a “0”; and another curve 32 shows how the output voltage varies asa function of the input voltage when the control signal CS is a “1”.

Inspection of curve 31 shows that on it, the high threshold voltageV_(TH) of the receiver occurs at a point 31 a. By definition, thethreshold voltage of the receiver is the input voltage which causes thereceiver output to be at its “1” output voltage divided by two.

At point 31 a, the receiver input voltage is 3.3 volts divided by 2; andthat is midway between the two input signal levels of 0 and 3.3 volts.Consequently, the noise margin NM0 between 0 volts and the highthreshold voltage, as well as the noise margin NM1 between 3.3 volts andthe high threshold voltage, are as large as possible.

Likewise, inspection curve 32 shows that the low threshold voltageV_(TL) occurs at a point 32 a. Here again, this threshold voltage is theinput voltage which causes the receiver output to be at its “1”outputvoltage level divided by two. At point 32 a, the receivers input voltageis 2.5 volts divided by 2. Consequently, the noise margin NNO′ between 0volts and the low threshold voltage, as well as the noise margin NM1′between 2.5 volts and the low threshold voltage, are as large aspossible.

From a systems viewpoint, the above feature of being able to shift thethreshold voltage of the receiver 11 is very important because itenables the chip 12 to be part of the data processing system which iseasily upgraded. For example, suppose -a) that the chip 12 is amicroprocessor chip on which the 3.3 volt receiver 11 is replicatedmultiple times and receives all of the signals for the microprocessor,and, that the 3.3 volt transmitter is likewise replicated multiple timeson a memory chip 22 which supplies data through the replicatedtransmitters to the microprocessor.

While a system with the above chips 12 and 22 is being marketed, anothermemory chip 23 could become available which has more memory cells thanthe memory chip 22 but which transmits its output signals with the 2.5volt transmitters 21. In that case, an upgraded system can be providedin which the memory chip 23 replaces the chip 22; and no loss in noisemargin will occur simply by switching the control signal CS from a “0”to a “1”. This is a major advantage since a new microprocessor chipwhich operates completely at 2.5 volts could take years to develop.

Turning now to FIG. 4, a preferred internal structure for the dualthreshold digital receiver circuit 11 will be described. As FIG. 4shows, that preferred structure includes one p-channel transistor T1 andthree n-channel transistors T2, T3, and T4. Transistors T1 and T2 areconnected in series between a supply voltage bus which carries 3.3volts, and a ground bus. Transistors T3 and T4 are connected in seriesto the connection between the two transistors T1 and T2, and the groundbus.

Input line 11 a which carries the input signal v_(i), is connected torespective gates on the transistors T1, T2, and T3. Output line 11 bwhich carries the output signal v_(o), is connected to the seriesconnection between transistors T1 and T2. And the control line 11 cwhich carries the control signal CS is connected to the gate ontransistor T4.

Also, each of the transistors T1-T4 has a channel with a particularwidth dimension and a particular length dimension. In FIG. 4, thesewidth and length dimensions are shown as a ratio where channel width isgiven in microns as the numerator, and channel length is given inmicrons as the denominator. Inspection of FIG. 4 shows that the channelwidth for transistors T1, T2, T3, and T4 respectively is 30 microns, 11microns, 55 microns, and 55 microns; whereas the channel length of eachof those transistors is 0.7 microns.

Due to the channel width/channel length ratios for the transistors T1and T2 as described above; the FIG. 4 receiver 11 will operate with thehigh threshold V_(TH) when the control signal CS is a “0”; and this modeof operation is illustrated in FIGS. 5A and 5B. By comparison, due tothe channel width/channel length ratios of the transistors T3 and T4 asdescribed above, the FIG. 4 receiver circuit 11 will operate with thelow threshold voltage V_(TL); and this mode of operation is illustratedin FIGS. 6A and 6B.

In FIG. 5A, the circuit of FIG. 4 is redrawn with the exception that thechannel of each of the transistors T1-T4 is shown to have a certainresistance. Transistor T1 has a channel resistance R1; transistor T2 hasa channel resistance R2; etc. Also in FIG. 4, the input voltage v_(i) isat the high threshold voltage level of 3.3 volts divided by 2; and thecontrol signal CS is a “0”.

Now the magnitude of the channel resistance of any one particulartransistor depends upon that transistors channel width, channel length,and gate voltage. If the gate voltage is such that the transistor isturned off, then the channel is an open circuit. If the gate voltageturns the transistor completely on, then the channel resistance isinversely proportional to the channel width and directly proportional tothe channel length. And, if the gate voltage only turns the transistorpartly on, then the channel resistance increases in an exponentialfashion from its fully turned value as the degree to which thetransistor is turned on decreases.

In FIG. 5A, the high threshold voltage of 3.3 volts divided by 2 on theinput line 11 a turns the transistors T1, T2, and T3 completely on; butthe control signal CS=0 turns transistor T4 completely off.Consequently, transistor T4 acts as an open circuit; and that nullifiesany effect of the resistance R3.

Thus, the circuit of FIG. 5A can be redrawn in a simplified fashion asshown in FIG. 5B. There, the output voltage v_(o) is equal to the supplyvoltage of 3.3 volts times a resistance ratio of R2÷(R1+R2).

These resistances R1 and R2 have equal magnitudes when the input voltagev_(i) is 3.3 volts÷2, and the channel width-length ratios are as givenin FIG. 4. There, transistor T1 is given a wider width in order tocompensate for the fact that a p-channel transistor is less conductivethan an n-channel transistor. Thus, when v_(i) is 3.3÷2 volts, v_(o) isalso 3.3÷2 volts.

Considering now FIG. 6A, it again illustrates the FIG. 4 circuit withthe modification that the channel of each of the transistors T1-T4 isshown to have a certain resistance. Here again, the magnitude of thechannel resistance of any one transistor depends upon the transistor'schannel width, channel length, and gate voltage.

In FIG. 6A, the input voltage v_(i) is 2.5 volts divided by 2. Thatinput voltage turns transistor T1 completely on, and it turnstransistors T2 and T3 only partly on. Consequently, transistor T1 has achannel resistance R1 which is the same as it was in FIG. 5B; whereastransistor T2 has a channel resistance R2 which is bigger than it was inFIG. 5B. In particular, the channel resistance R2 for transistor T2 inFIG. 6A is about 5.2 times its resistance in FIG. 5B.

Recall from FIG. 4 that transistor T3 has a channel which is about fivetimes wider than the channel of transistor T2. Consequently in FIG. 6A,the channel resistance R3 is about one-fifth the channel resistance R2.

Transistor T4 in FIG. 6A has a gate voltage of CS=“1”; and thustransistor T4 is completely turned on. Also, the channel of transistorof T4 is about five times wider than the channel of transistor of T2.Consequently, in FIG. 6A, the channel resistance R4 is about one-fifthof the fully turned on channel resistance of transistor T2 or R1÷5.

Next, the circuit of FIG. 6A can be simplified to the circuit of FIG. 6Bby combining the resistances R3 and R4 into one series resistance; andby combining that series resistance in parallel with resistance R2. Suchresistance combining steps yield an equivalent resistance R_(eq) which,as FIG. 6B shows, is approximately equal to R1.

In FIG. 6B, the output voltage v_(o) is equal to the supply voltage of3.3 volts times a resistance ratio of R_(eq)÷(R1+R_(eq)). In that ratio,the resistance R_(eq) equals R1; and thus the resulting ratio isapproximately equal to one half. Consequently, when the input voltagev_(i) is 2.5 volts divided by 2, the output voltage v_(o) is equal to3.3 volts divided by 2.

One preferred embodiment of the invention has now been described indetail. In addition however, various changes and modifications can bemade to the above described details without departing from the natureand spirit of the invention.

For example, as one particular modification, the channel width ratiosfor transistors T3 and T4 can be changed so long as, under the inputsignal conditions the FIG. 6A, the total series resistance of R3+R4remains equal to 6.2R1÷5. In other words, in FIG. 6A, the channelresistance R3 can be decreased so long as the channel resistance R4 isincreased by the same amount; and vice versa.

To illustrate the above modification, FIG. 7 includes a table whichgives several alternative channel width-length ratios for thetransistors T3 and T4. In column Cl, the channel width-length ratioswhich are given for the transistors T3 and T4 correspond to those whichwere specified in FIG. 4. By comparison, in column C2, the channel widthof transistor T3 is increased to 65 microns; and that causes the partlyon channel resistance R3 in FIG. 6A to decrease. Consequently, tocompensate for the decrease in the R3 channel resistance, the channelwidth of transistor T4 is decreased to 40 microns.

Likewise, in column C3 of FIG. 7, the channel width of transistor T3 isdecreased to 45 microns; and that causes the partly on channelresistance R3 in FIG. 6B to increase. Consequently, to compensate forthat increased channel resistance, the channel width of transistor T4 isincreased to 85 microns.

In column C4, the channel length of transistor T3 is increased to 0.8microns; and that causes the partly on channel resistance R3 in FIG. 6Ato increase. To compensate for that increased channel resistance, thechannel width of transistor T4 is increased to 75 microns.

Lastly, in column C5, the channel length of transistor T4 is increasedto 0.8 microns; and that causes the channel resistance R4 in FIG. 6A toincrease. To compensate for that increase in the channel resistance R4,the channel width of transistor T3 is increased to 75 microns.

Further, as to another modification, the low threshold voltage V_(TL) ofthe FIG. 4 circuit is not limited to 2.5 volts÷2. Instead, that lowthreshold voltage can be further reduced by decreasing the total serieschannel resistance R3+R4 under the conditions where the control signalCS equals a “1” and the input voltage v_(i) equals the new low thresholdvoltage.

For example, suppose a new low threshold voltage of 1.7 volts÷2 isrequired. In that case, the total channel resistance R3+R4 of FIG. 6Aneeds to be reduced such that when the input signal v_(i) equals 1.7volts÷2, the output voltage v_(o) equals 3.3 volts÷2. Such a reductionof the channel resistance R3+R4 may be achieved by increasing thechannel width and/or decreasing the channel length of one or both of thetransistors T3 and T4; and various suitable channel dimensions may beselected through computer simulation.

Also, as still another modification, a fifth transistor (not shown) canbe added in parallel with transistor T4 of FIG. 4, and a second controlsignal can be applied to fifth transistor's gate. With thatmodification, the resulting circuit will have a high threshold voltageand a low threshold voltage as previously described; and in addition, itwill have a new “very low” threshold voltage.

To select the new very low threshold voltage, both the fifth transistorand transistor T4 are fully turned on with their respective controlsignals. This lowers the total channel resistance which is in serieswith transistor T3; and that in turn lowers the threshold voltage of thereceiver as was explained above.

Accordingly, in view of all of the above modifications which can be madeto the preferred embodiment of FIG. 4, it is to be understood that theinvention is not limited to just that one particular embodiment but isdefined by the appended claims.

What is claimed is:
 1. A method of converting one set of input signalsof 0 and 3.3 volts, and another set of input signals of 0 and 2.5 voltsinto one set of output signals of 0 and 3.3 volts such that noise marginis maximized; said method being performed by a circuit having first andsecond transistors in series from a first bus at 3.3 volts to a secondbus at 0 volts, and having third and fourth transistors in series froman output node between said first and second transistors to said secondbus; said method including the steps of: receiving said one set of inputsignals on an input which is coupled to respective gates in said first,second, and third transistors while a control signal of 0 volts isapplied to a gate in said fourth transistor; and subsequently receivingsaid another set of input signals on said input while a control signalof 3.3 volts is applied to said gate in said fourth transistor;selecting said transistors with respective turn-on voltages such that:a) said first and second transistors enter a fully-on state and saidfourth transistor enters a fully-off state when said input signal ishalfway to 3.3 volts and said control signal is at 0 volts; and, b) saidfirst and fourth transistors enter said fully-on state and said secondand third transistors enter a partially-on state when said input signalis half-way to said 2.5 volts and said control signal is at 3.3 volts;further selecting said transistors with respective channel lengths andwidths such that: a) said first, second and fourth transistors haverespective channel resistances in said fully-on state of R1_(ON),R2_(ON) and R4_(ON); b) said second and third transistors haverespective channel resistances in said partially-on state of R2_(PON)and R3 _(PON), both of which vary exponentially with gate voltage; and,c) R2_(ON) equals R1_(ON), and R2_(PON) in parallel with R3_(PON) plusR4_(ON) equals R1_(ON).
 2. A method of converting one set of inputsignals with zero and high voltage levels, and another set of inputsignals with zero and intermediate voltage levels, into one set ofoutput signals with zero and said high voltage levels such that noisemargin is maximized, said method being performed by a circuit havingfirst and second transistors in series from a first bus at said highvoltage level to a second bus at zero volts, and having third and fourthtransistors in series from an output node between said first and secondtransistors to said second bus; said method including the steps of:receiving said one set of input signals on an input which is coupled torespective gates in said first, second, and third transistors while acontrol signal at zero volts is applied to a gate in said fourthtransistor; and subsequently receiving said another set of input signalson said input while a control signal at said high voltage level isapplied to said gate in said fourth transistor; selecting saidtransistors with respective turn-on voltages such that said first andsecond transistors enter a fully-on state and said fourth transistorenters a fully-off state when said input signal is halfway to said highvoltage level and said control signal is at zero volts; and said firstand fourth transistors enter said fully-on state and said second andthird transistors in a partially-on state when said input signal ishalf-way to said intermediate voltage level and said control signal isat said high voltage level; further selecting said transistors withrespective channel lengths and widths such that: a) said first, secondand fourth transistors have respective channel resistances in saidfully-on state of R1_(ON), R2_(ON) and R4_(ON); b) said second and thirdtransistors have respective channel resistances in said partially-onstate of R2_(PON) and R3_(PON), both of which vary exponentially withgate voltage; and, c) R2_(ON) equals R1_(ON), and R2_(PON) in parallelwith R3_(PON plus R)4_(ON) equals R1_(ON).
 3. A method according toclaim 2 wherein said high voltage level is 3.3 volts and saidintermediate voltage level is 2.5 volts.
 4. A method according to claim2 wherein said high voltage level is 3.3 volts and said intermediatevoltage level is 1.7 volts.
 5. A method according to claim 2 whereinsaid third transistor and said fourth transistor have respectivechannels with equal lengths and equal widths.
 6. A method according toclaim 2 wherein said third transistor and said fourth transistor haverespective channels with equal lengths and widths which differ from eachother.
 7. A method according to claim 2 wherein said third transistorand said fourth transistor have respective channels with lengths whichdiffer substantially from each other and widths which differ from eachother.